Sean Finney   				Writeup for CS23 Lab 3.
Kuzman Ganchev
Feng He

ABSTRACT

   In this lab we implemented a CPU with the instruction set described in
   the lab instructions. These include a number of logical and arithmetic
   operations as well as control instructions to read and write to an I/O
   port, read from and write to internal registers and to perform
   conditional and unconditional branches. The CPU does not implement
   floating point opeartions natively, nor does it implement instructions
   for calling of subroutines or multiplication and division. It has a
   native word length of 8 bits. Internally the CPU is an ALU embedded in
   a state machine that contains all of the control logic as well as the
   dataflow design and an interface to a ROM. The ALU is a simple
   combinatorial circuit, defined by a behavioral VHDL description. The
   state machine, is also defined in VHDL and has an interface to a ROM
   that stores the program to be executed.  In addition, we also created
   a small utility to assemble instructions into a .mif ROM for use with
   this or any other project.

1. If you were going to re-design this computer, would you force the
    data path through the ALU every cycle? What are the advantages and
    disadvantages of this design?

   If we do not force the data through the ALU, then we can
   eliminate the execute cycle for those instructions that do not
   need to use the ALU. This is 5/16 instructions.  Unfortunately
   this would involve adding the logic to decide whether the current
   instruction needs to be passed to the ALU. Not having a constant
   execution time is also a disadvantage in and of itself, since it
   complicates estimating the execution time for a sequence of
   instructions.


2. If you were going to re-design this computer, what instructions
   would you add to this set? Why?

   To start off with there are several instructions that are
   unsymmetrical. We have instructions for "shift right logical",
   "shift right arithmetic" "shift left logical" but no "shift left
   arithmetic". Also there is a branch on zero for address but no
   branch on negative for an address (there are both branch on zero
   and branch on negative for an offset). Implementing these
   instructions would be the first step. Ideally, we would want to
   have a full-functionality instruction set including instructions
   for multiplication, division, subroutine calling and a RAM (or at
   least an interface to a writable memory). We would also ideally
   like to implement some method for handling interrupts.


3. If you were going to re-design this computer, would you make the
   ALU more complex? How?

   We would include multiplication and division instructions to the
   ALU. Other than that, the ALU implements most of the instructions
   one would want.


4. How would you modify the above design to include a check for
   interrupts?

   We would need to add an interrupt request input signal, as well
   as adding extra registers to store the state when the interrupt
   request was issued. The control logic would be similar to the
   control logic for a call instruction, where the CPU has to be
   able to return to the correct state after the subroutine is
   complete.

5. How would you pipeline this architecture?

   One fairly simple way to pipeline this machine is the
   following. We already have logic to determine whether we should
   write to the PC. In the case that we do not, we can overlap the
   fetch of the next instruction with the store of the current one
   (we can increment the PC during the execute cycle). If we do
   write to the PC, then we have to do a separate fetch for the next
   instruction, but if the PC does not get written to, we can go
   from the store of one instruction to the the decode of then next.